QD of the counter when inverted forms the clock to the 8-Bit shift register 74LS164. This clock is fed to the 74LS93 4-bit binary counter. The 555 timer sets-up the primary clock at 2400 Hz. The circuit is implemented using standard TTL devices a 555 timer and an ULN2003 open-collector driver. I wish to acknowledge the use of the online OMNI LFSR calculator used in verification of the hardware results. This is suggested as a starter project to students for implementation on FPGA kits where both the LFSR and serial-data output are implemented. Generation of different length PN sequences including the maximally long LSFR could be demonstrated and compared with calculated results. This permitted acquiring and analyzing the output stream using a simple dumb terminal.Ī 8-bit DIP switch permits setting up of desired feedback combinations from the eight shift register outputs. Additional circuitry was added to convert and send the 1's and 0's output of the LFSR as ASCII serial data '30','31' Hex. This project implements a pseudo-random (PN) sequence generator based on a 8-bit linear-feedback shift register (LFSR). Surprisingly the breadboard hardware which was recently returned to me and had not been powered for 30 odd years worked perfectly when powered ON. This is revisit of a student project I mentored back in 1990-91.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |